形式等效性檢查
形式等效性檢查[1]（英語：formal equivalence checking）是電子設計自動化的一個步驟，通常是在集成電路設計中，通過一些數學方法（如二元決策圖、布爾可滿足性問題），來對不同電路之間進行形式驗證，比較它們在行為上是否等效。
參考文獻
- Electronic Design Automation For Integrated Circuits Handbook, by Lavagno, Martin, and Scheffer, ISBN 0-8493-3096-3 A survey of the field. This article was derived, with permission, from Volume 2, Chapter 4, Equivalence Checking, by Fabio Somenzi and Andreas Kuehlmann.
- R.E. Bryant, Graph-based algorithms for Boolean function manipulation, IEEE Transactions on Computers., C-35, pp. 677–691, 1986. The original reference on BDDs.