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記憶體層級平行

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記憶體層級平行(英語:Memory-level parallelism,縮寫為 MLP'),平行計算技術的一種,是電腦架構的一種,能夠同時進行數個記憶體操作,特別是在快取未命中(cache miss),或轉譯後備緩衝區未命中(TLB miss)時。

在整塊性核心處理器架構下,記憶體層級平行可以被視為是一種特殊的指令層級平行(ILP)。它也經常在超純量架構下出現。

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參考文獻

  • "Enhancing memory level parallelism via recovery-free value prediction." H. Zhou and T. M. Conte. Proceedings of the 17th Annual International Conference on Supercomputing, ICS 2003.
  • "A Case for MLP-Aware Cache Replacement", Moinuddin K. Qureshi, Daniel N. Lynch, Onur Mutlu, Yale N. Patt. Proceedings of the 33rd annual International Symposium on Computer Architecture (ISCA), 2006.
  • "MLP-Aware Runahead Threads în a Simultaneous Multithreading Processor"(paper). Craeynest, K. Van, S. Eyerman, L. Eeckhout. Proc. of The 4th HiPEAC Int. Conf., Paphos, Cyprus, January 2009.
  • "Microarchitecture optimizations for exploiting memory-level parallelism", Yuan Chou, B. Fahs, and S. Abraham, Computer Architecture, 2004. Proceedings. 31st Annual International Symposium on 2004.
  • "Coming challenges in microarchitecture and architecture", Ronen, R.; Mendelson, A.; Lai, K.; Shih-Lien Lu; Pollack, F.; Shen, J.P. Proceedings of the IEEE Volume: 89 Issue: 3 Mar 2001
  • "MLP yes! ILP no!" (abstract頁面存檔備份,存於互聯網檔案館) / slides頁面存檔備份,存於互聯網檔案館)), A. Glew. In Wild and Crazy Ideas Session, 8th International Conference on Architectural Support for Programming Languages and Operating Systems, October 1998.